Lattice Diagrams Using Reed Muller Logic

Universal Akers Arrays (UAA) allow to realize arbitrary Boolean function directly in cellular layout but are very area-ine cient. This paper presents an extension of UAAs, called \Lattice Diagrams" in which Shannon, Positive and Negative Davio expansions are used in nodes. An e cient method of mappig arbitrary multi-output incompletely speci ed functions to them is presented. We prove that with these extensions, our concept of regular layout becomes not only feasible but also e cient. Regular layout is a fundamental concept in VLSI design which can have applications to submicron design and designing new ne-grain FPGAs.